1. Field of the Invention
The present invention relates to a semiconductor device, and a method for producing the same. More particularly, the present invention relates to a semiconductor device including a field effect transistor, and a method for producing the same.
2. Description of the Background Art
In recent years, semiconductor devices have been more and more integrated and more and more miniaturized, and transistors have also been miniaturized rapidly. Accordingly, the thickness of the gate insulating film of the transistor has been reduced, and it is now as small as about 2.0 nm or less in terms of the EOT (equivalent oxide thickness). When the thickness thereof is reduced, a conventional SiO2 gate insulating film will have an increased, non-negligible leak current. Thus, a high dielectric constant film (hereinafter referred to as a “high-k film”) is used as the gate insulating film. By using a high-k film as the gate insulating film, it is possible to reduce the EOT and reduce the power consumption while ensuring a large physical thickness to thereby suppress the tunnel current.
As transistors are miniaturized, there is a problem with the gate electrode that the capacitance decreases due to the depletion of the electrode. For a conventional polysilicon gate electrode, this capacitance decrease accounts for an about 0.5 nm increase in the thickness of the silicon oxide film, which is non-negligible with respect to the thickness of the gate insulating film. Therefore, for the gate electrode, it has been proposed in the art to use a metal, instead of polysilicon used in the prior art. With a metal gate, it is possible to suppress the depletion problem as described above.
With a gate electrode using a polysilicon film as in the prior art, it is easy to separately produce a p-channel region and an n-channel region, i.e., regions of two different work functions, by using a photolithography method and an ion implantation method. For example, when forming a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) in which a polysilicon film is used for the gate electrode, there is a widely-used method in the art (dual work function), in which n+ PolySi is used for the gate electrode of an nMOSFET and p+ PolySi for the gate electrode of a pMOSFET, thereby realizing a low threshold.
With a metal gate, however, no method has been established in the art, equivalent to the above-described method for a polysilicon gate, in which a single type of a film is deposited, after which impurities of different conductivity types are implanted into appropriate regions, thereby easily realizing variations of the work function.
In view of this, a hybrid metal gate electrode structure has been proposed in the art as a gate electrode structure with which a dual work function control is realized while using a metal gate electrode. Specifically, in this gate electrode structure, a pMIS (Metal Insulator Semiconductor) structure with a metal gate is used on the p-channel side for suppressing the depletion as described above, whereas an nMOS structure with n+ PolySi, with which the work function can easily be controlled, is used on the n-channel side where the depletion of the gate electrode is less likely to occur (see Non-Patent Document 1).
A method for forming a CMOSFET using conventional hybrid metal gate electrode structure will now be described.
FIGS. 23A, 23B, 24A and 24B are cross-sectional views each showing a step in a method for forming a CMOSFET using a conventional hybrid metal gate electrode structure.
First, as shown in FIG. 23A, an isolation region 12 is formed in a semiconductor substrate 11 to thereby separate an n-channel region 13 and a p-channel region 14 from each other, after which a p well and an n well (not shown) are formed in the n-channel region 13 and the p-channel region 14, respectively. Then, a high-k film such as an HfO2 film is formed as a gate insulating film 15 on the semiconductor substrate 11 including the regions 13 and 14. Then, a gate electrode material film 21 of TiN, or the like, which is a metal containing film for the pMIS structure, is deposited on the gate insulating film 15.
Then, as shown in FIG. 23B, a portion of the gate electrode material film 21 in the n-channel region 13 is selectively removed by using a resist pattern 19 having an opening corresponding to the n-channel region 13, and then the resist pattern 19 is removed. Then, as shown in FIG. 24A, a polysilicon film 23 is deposited across the entire surface of the semiconductor substrate 11, and then a resist pattern 24 covering gate electrode formation regions is formed.
Then, the polysilicon film 23 in the n-channel region 13 and a multi-layer film of the gate electrode material film 21 and the polysilicon film 23 in the p-channel region 14 are processed into gate electrode patterns, by using the resist pattern 24. Thus, as shown in FIG. 24B, a gate electrode 51 being the polysilicon film 23 is formed in the n-channel region 13, and a gate electrode 52 being a multi-layer film of the gate electrode material film 21 and the polysilicon film 23 is formed in the p-channel region 14. Then, although not shown in the figure, the n-channel region 13 and the p-channel region 14 are subjected to an ion implantation through an ordinary process, by using the gate electrodes as a mask, to thereby form source/drain regions, followed by a heat treatment for activating the impurity.
Non-Patent Document 1: Y. Nishida, et al., Advanced Poly-Si NMIS and Poly-Si/TiN PMIS Hybrid-gate High-k CMIS using PVD/CVD-Stacked TiN and Local Strain Technique, 2007, Symposium on VLSI Technology Digest of Technical Papers, pp. 214-215